1. Field of the Invention
The invention relates to semiconductor devices, and more specifically, to semiconductor devices capable of avoiding latch-up.
2. Description of the Related Art
Latch-up effect is common in Complementary Metal Oxide Semiconductor (CMOS) devices. The main reason of the formation of the latch-up effect is that parasitic Silicon Controlled Rectifier (SCR) component between the N-type Metal Oxide semiconductor (NMOS) and the P-type Metal Oxide Semiconductor (PMOS) has been trigged. Once the parasitic SCR component has been triggered, unintended high-current will be generated, thereby affecting the normal operation of the semiconductor device even further causing the wafer to be put too much current and burned.
FIG. 1A is a schematic diagram of a conventional CMOS device 10. The CMOS device 10 comprises a P-type substrate 100, a P-type well region 102 and a N-type well region 104 formed on the P-type substrate 100, a P+-type doped region 110 and a N+-type doped region 111 formed on the P type well region 102, and a P+-type doped region 112 and a N+-type doped region 113 formed on the N-type well region 104. As shown in FIG. 1A, the CMOS device 10 has a pair of parasitic Bipolar Junction Transistors (BJT), namely the parasitic PNP-type BJT Q1 and the parasitic NPN-type BJT Q2. The parasitic BJTs Q1 and Q2, the resistance RNW of the N-type well region 104 and the resistance RPW of the P-type well region resistance 102 form the parasitic SCR component 140 as shown in FIG. 1B. When the parasitic SCR component 140 is triggered, the parasitic NPN-type BJT Q2 is turned on to generate the base current, and the base current will flow through the parasitic PNP-type BJT Q1 such that the collector voltage of Q1 rises to over the turn-on voltage, thereby turning on the parasitic PNP-type BJT Q1. After the parasitic PNP-type BJT Q1 is turned on, the base current is generated, and will then flow through the parasitic NPN-type BJT Q2 and generate more current. Such positive feedback phenomenon may cause the current to be increased repeatedly, leading to damage of the semiconductor device.
Taking a power circuit as an example in the following for illustrating how the parasitic SCR component in the CMOS device is triggered. FIG. 2A is a circuit diagram of a conventional power circuit. The power circuit includes the power PMOS transistor P1, the Electrostatic Discharge (ESD) NMOS transistors N1, the resistor R and the output terminal VOUT. FIG. 2B is a circuit diagram of a conventional power circuit under the short circuit test (SCT). As shown in FIG. 2B, in the short circuit test, the output terminal VOUT is connected to the ground, resulting in a negative bias. While this negative bias falls into the emitter of the parasitic NPN-type BJT Q2, as shown in FIG. 2C, the parasitic NPN-type BJT Q2 is turned on and a current INMOS is generated, and the parasitic PNP-type BJT Q1 is then turned on accordingly, thus the latch-up current is generated and causes damage to the power circuit components.
Thus, there is a need for the development of the semiconductor device to avoid occurrence of the latch-up.